Europe Takes Another Whack At Homegrown Compute Engines

With RISC-V International, the body controlling the RISC-V instruction set, located in Switzerland for the past five years, RISC-V now has just as much right to call itself indigenous to Europe as does Arm Ltd, the British chip company that finds itself on the other side of the English Channel after the Brexit break up and that is still around 90 percent owned by Japanese conglomerate SoftBank.

A credible argument can indeed be made that the RISC-V architecture is more open than the Arm architecture and that it is the logical successor to Arm given its royalty free licensing and its ability to be licensed around the world thanks to not being under the export control thumb of the US government, which would not have been the case had the organization stayed in Silicon Valley, its birthplace.

Given the economics – RISC-V by definition is less expensive than Arm – and the fact that RISC-V is the natural successor to the Arm architecture (or possibly the X86 architecture that we think will persist for decades at least), it is not hard to think RISC-V has an increasingly probably future in the datacenter. Factor in that China wants to have an indigenous architecture for compute engines, and you can see why Arm Is The New RISC/Unix, RISC-V Is The New Arm, as we put it back in September 2022.

Given the difficulties in getting homegrown Arm processors out the door through the European Processor Initiative – despite the best efforts of chip startup SiPearl and its “Rhea” line of Arm server processors, which could have used quite a bit more funding from the European Union to get the job done quicker – it is no surprise that Europe is going to have another go at it with the DARE project, short for Digital Autonomy with RISC-V in Europe and what we will simply call the Dare project going forward because we don’t like shouty abbreviations in this publication.

Project Dare is very much focused on HPC even if it does have potential AI use cases. The project is being funded by the EuroHPC Joint Undertaking, the same pan-European organization that has funded pre-exascale and exascale systems across the European continent. A total of 38 different organizations, which are detailed in the right side of the chart below, have joined up to work collaboratively on three different RISC-V compute engines:

The Dare effort is being coordinated by the Barcelona Supercomputing Center, one of the big proponents of Arm-based compute engines in HPC, and will leverage experience from the prior European Processor Initiative, MEEP, eProcessor, EUPILOT, and EUPEX projects, all of which had a hand in trying to create indigenous computation that, while successful in their own ways, have not really moved the needle much. Most of the HPC systems in Europe are based on engines from Intel, AMD, and Nvidia, all based in the United States. Shifting from the Arm ISA to the RISC-V ISA not only allows Europe to potentially cut its costs for creating chips in the HPC and AI arena, but it also allows Europe to intersect with a future that is inevitably coming further down the road rather than trying to catch up with a past that has already happened.

What is also different this time around is money, but there is a question of whether or not even the substantially larger funds will be enough. SiPearl, which is spearheading Arm CPUs for HPC and AI in Europe, got €6.2 million in seed funding back in 2019 from the European Processor Initiative, and raised €90 million in Series A funding back in April 2023 to take the Rhea project up another level. (This was a total of about $105 million, and with other grants from the EPI effort, it pulled in a total of $120.5 million.) SiPearl had to go raise the Series A itself. Contrast this with the €8 billion EuroHPC Joint Undertaking that is part of the European Horizon 2020 program. There is a lot of money for systems, and not a lot for compute engine development and none for networking as far as we can see. (More on that in a moment.)

The member nations of the European Union are putting up  €120 million for the Dare effort, with a matching  €120 million out of the EuroHPC JU budget that has already been allocated, for a total of €240 million ($259.9 million at current exchange rates between the US dollar and the European euro). This sounds like a lot of money until you realize the first phase of the Dare project, called Specific Grant Agreement 1, will be covered by that €240 million and will span three years. Dare is the culmination of a call for developing an HPC ecosystem based on RISC-V that was put out in February 2023, and it will have multiple phases running put to 2030. It is not clear what the funding level will be for those six years.

SiPearl is not being put in charge of the RISC-V general purpose processor development, but Codasip, a processor design company founded by Karel Masařík in 2014 in Munich, Germany that was one of the founders of the RISC-V International consortium, is being tasked with this effort.

Last year, Codasip finished up a 64-bit RISC-V chip called the X730, with a nifty set of security protocols built in called CHERI, that you can license today. And the company sells a product called Codasip Studio, a tool to customize the RISC-V cores. The company has raised $34.6 million in total funding in the past decade, including money from various EU initiatives as well as a seed round of $2.5 million in 2016 and a Series A of $10 million in 2018.

Openchip and Software Technologies, a spinoff of the Barcelona Supercomputing Center in Spain, was founded last year, and it is in charge of creating a vector compute engine. Francesc Guim, an HPC researcher at BSC who also worked at Intel’s Data Center & AI group for six years, is the company‘s chief executive officer. Gaspar Mora, chief technology officer at Openchip, did a stint building network-on-chip interconnects at Intel before working on the Omni-Path HPC interconnect. He moved to Nvidia in 2020 and worked on GPU memory subsystems. The company’s chief silicon architect, Violante Moschiano, worked for most of the past two decades at Micron Technology, where he rose to be a Fellow.

As you all well know, vector math is particularly important in HPC and is also sometimes important in AI.

The third chip to be created under the Dare initiative is called the AI Processing Unit, or AIPU, and it will be focused on doing AI inference, not AI training. Axelera AI, founded in 2021 in Eindhoven, the Netherlands, will be designing this AI inference processor. Fabrizio Del Maffeo, the company’s co-founder and chief executive officer, has long experience in the embedded and edge AI space and has amassed $203.2 million in funding for Axelera AI thus far. Axelera AI has secured €61.6 million in funding for the development of its “Titania” Ai inferencing chip, so that accounts for that piece of the €240 million that Europe is ponying up for the Dare project.

All three compute engines will use a chiplet approach, which increases complexity but also increases flexibility and improves yields on chips, which is especially important on lead-edge manufacturing nodes at Taiwan Semiconductor Manufacturing Co.

We wonder if total of €240 million for creating three chips is enough, given what the likes of Nvidia, AMD, and Intel spend to make their compute engines.

And we also wonder why the Dare effort also does not include networking, which is also not indigenous to Europe and needs to be if economic and technical independence is so valued. Europe would seem to need its own high bandwidth, low latency implementation of an Ultra Ethernet Consortium switch ASIC as well as a companion SmartNIC/DPU to go with that switch.

And finally, we wonder what the United Kingdom will do, and what it can do, to join the Dare effort.

Dare is not just about hardware, of course. Imec is being tasked with integration and prototyping, and the Jülich Supercomputing Center (JSC) along with the Barcelona Supercomputing Center (BSC) will be working together on application and system software for these three devices.

Presumably, the goal is to have compute engines ready for the next round of exascale-class supercomputers, which are expected in the 2028 through 2030 timeframe.